1. Field of the Invention
The present invention relates to semiconductor devices and a method for fabricating semiconductor devices, and more particularly, to a semiconductor device and a method for fabricating the semiconductor device in order to prevent impurities, such as a contaminant or residue, from being generated within a contact of a load resistor.
2. Description of the Related Art
Generally, a load resistor is arranged in the peripheral areas of a semiconductor device, such as a dynamic random access memory (DRAM). The load resistor, mainly comprised of a plate poly silicon layer (P-Poly) or a metal pattern, may vary in length from a few micrometers (μm) to hundreds of micrometers (μm). Such a load resistor is insulated electrically and physically.
A long load resistor, which is applied to a semiconductor device as a plate poly-silicon layer (P-Poly), is insulated by the application of an insulation layer. In such a configuration, contacts (e.g., metal contacts) are fabricated at both ends of the load resistor to connect the load resistor to a metal pattern deposited above the insulation layer.
In the electrical circuit of the semiconductor device, such contacts have the important role of connecting a layer with another heterogeneous layer, for example, connecting a poly-silicon layer with a metal pattern. As the semiconductor device becomes increasingly integrated, the aspect ratios, i.e., the ratios of length to width, of the contacts increase. Therefore, each contact becomes narrower, making it difficult to perform an etching process because of the tight margin of the contact fabrication.
FIGS. 1A and 1B illustrate planar and cross-sectional views of a prior art structure in which metal patterns 140 are connected to a long load resistor 110 through metal contacts 130 according to the prior art.
Referring to FIGS. 1A and 1B, a load resistor 110 is relatively long with respect to its length and width. Such a load resistor 110 has a winding shape on a semiconductor substrate 100. After the load resistor is fabricated on the semiconductor substrate 100, an insulation layer 120 is deposited on the substrate 100 above of the load resistor 110. A dry-etching process is applied to the insulation layer 120, in order to expose both ends of the load resistor 110 to fabricate contact holes. A contact plug 135 fills each of the contact holes to form contacts 130 with the load resistor 110. The contact plug 135 is fabricated from a conductive material, such as tungsten (W), tungsten silicide (WSi), poly-silicon, or aluminum (Al). A metal pattern 140 is then formed over the substrate 100 and in contact with contact plugs 135.
As discussed above, the conventional process of electrically connecting a metal pattern 140 to the load resistor 110 involves using a dry-etching process to create the contact hole, which is filled with the contact plug 135. During this process, plasma ions or etching residues accumulate on the surface of the load resistor 110.
FIG. 2 is an image captured by a scanning electron microscope (SEM), which shows contacts 231 and 232 fabricated on load resistors of a plate poly-silicon layer according to the conventional process. Referring to FIG. 2, contacts 231 are placed at both ends of a poly-silicon layer (load resistor) with a considerably small length, and contacts 232 are placed at the ends of a considerably long poly-silicon layer. No significant electric charge build up occurs within the contacts 231 of the considerably short poly-silicon layer. However, a significant electric charge build up occurs within the contacts 232 at both ends of the considerably long poly-silicon layer. The accumulated electric charge in the contacts 232 results from local concentrations of electric charge, which occur during the plasma etching process of an insulation layer 120. During the plasma etching process, the considerably long load resistor 110 under the insulation layer 120 has a floating electrical state.
As described above, the accumulation of electric charge depends on the length of the load resistor. In the case of plate poly silicon layer with sheet resistance of 60 Ω/cm2 and width of 1.7 μm, an electric charge does not build up when the length of the load resistor is 9,000 μm. However, a build up of electric charge will occur when the length of the load resistor is 16,000 μm.
FIG. 3 is an image captured by a transmission electron microscope TEM, which illustrates impurities, such as an insulating material, that are generated between the load resistor and the contact plug by the electric charge build up that occurs in the prior art.
Referring to FIG. 3, plasma ions or etching residues generated by the electric charge build up during the application of a plasma etching process to an insulation layer E. This transforms the physical and chemical characteristics of the interface between the load resistor and the contact plug, thereby generating impurities, such as an insulating material D. Therefore, the electric charge build up degrades the conductivity of the interface between the load resistor and the contact plug, not only making it difficult to obtain a fine contact characteristic, but also altering electric potentials and creating abnormal contact profiles.